PIC18F6410-I/PT【PDF 83/411 页】IC PIC MCU FLASH 8KX16 64TQFP

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Sheet目录3840

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2010-2012 Microchip Technology Inc.

DS39977F-page 173

PIC18F66K80 FAMILY

11.1.3

OPEN-DRAIN OUTPUTS

The output pins for several peripherals are also

equipped with a configurable, open-drain output option.

This allows the peripherals to communicate with

external digital logic, operating at a higher voltage

level, without the use of level translators.

The open-drain option is implemented on port pins

specifically associated with the data and clock outputs

of the USARTs, the MSSP module (in SPI mode) and

the CCP modules. This option is selectively enabled by

setting the open-drain control bits in the ODCON

When the open-drain option is required, the output pin

must also be tied through an external pull-up resistor

provided by the user to a higher voltage level, up to 5V

(Figure 11-2). When a digital logic high signal is output,

it is pulled up to the higher voltage level.

FIGURE 11-2:

USING THE OPEN-DRAIN

OUTPUT (USARTx SHOWN

AS EXAMPLE)

TXX

+5V

3.3V

(at logic ‘1’)

3.3V

VDD

PIC18F66K80

REGISTER 11-3:

ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER

R/W-0

SSPOD

CCP5OD

CCP4OD

CCP3OD

CCP2OD

CCP1OD

U2OD

U1OD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SSPOD:

SPI Open-Drain Output Enable bit

= Open-drain capability is enabled